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Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain | IEEE Conference Publication | IEEE Xplore

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain


Abstract:

This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage const...Show More

Abstract:

This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250 Ksamples/s and 2 Msamples/s, at a supply voltage of 260 mV. The total energy dissipation of the filter is 205 fJ per sample.
Date of Conference: 15-18 May 2011
Date Added to IEEE Xplore: 04 July 2011
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Conference Location: Rio de Janeiro, Brazil

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