A low-power 8-bit SAR ADC for a QCIF image sensor | IEEE Conference Publication | IEEE Xplore

A low-power 8-bit SAR ADC for a QCIF image sensor


Abstract:

In this paper, we report on an 8-bit auto-calibrating successive-approximation-register (SAR) analog-to-digital converter (ADC) for ultra-low power image sensors. The fab...Show More

Abstract:

In this paper, we report on an 8-bit auto-calibrating successive-approximation-register (SAR) analog-to-digital converter (ADC) for ultra-low power image sensors. The fabricated design includes an on-chip bandgap voltage reference and a tunable clock generator in addition to the SAR ADC core circuitry. Aside from two power pins, the design uses only one extra pin to output the digitized samples serially. Power consumption for the design is 21μW at 0.8V supply voltage, and it is 32μW including ancillary circuits. The sampling rate varies from 370kS/s to 1.6MS/s depending on the supply voltage. The design occupies an area of 0.2mm2 in a 0.18μm CMOS process, of which 0.073mm2 is for the SAR ADC core.
Date of Conference: 15-18 May 2011
Date Added to IEEE Xplore: 04 July 2011
ISBN Information:

ISSN Information:

Conference Location: Rio de Janeiro, Brazil

Contact IEEE to Subscribe

References

References is not available for this document.