Reliability of CMOS devices emerges as a vital design constraint, evidenced by several CMOS failure mechanisms. Such mechanisms have traditionally been modeled independently, using statistical approximation techniques to estimate Mean-Time-to-Failure (MTTF) rates. This paper proposes a unified framework that integrates the existing failure models into a multi-objective optimization engine, in an attempt to provide a pareto-optimal solution indicating the suggested operating conditions of a system for a given technology and size (in transistors), in an effort to maximize its lifetime reliability. In addition to the existing failure mechanisms, the framework also considers a proposed system-level leakage power estimation model, as leakage is interdependent on temperature, and as such impacts system reliability. The framework can be used in several design scenarios, such as thermal-aware task scheduling.