A time-multiplexed row-parallel architecture is pro- posed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) of images and video sequences. The architecture is based on the Arai algorithm with AI encoding. This leads to an 8×8 2-D DCT which is entirely free of quantization errors. The error free coefficients may be converted into a regular arithmetic format using a final reconstruction step (FRS) at the output stage. The accuracy of the FRS allows each of the 64 coefficients to have its precision set independent of other coefficients without the leakage of quantization noise between coefficient channels. Our architecture leads to low-noise applications in digital video compression, coding, and other image processing applications that rely on the fast systolic computation of the 2-D DCT. A prototype of the 2-D DCT is physically realized, tested, and verified on chip, using a Xilinx Virtex-4 S×35-10ff668 device. The maximum clock rate was F_clock = 121 MHz, implying an equivalent frame sample rate of 466 Hz, for an image frame size of 1920 × 1080, which is a common high definition video format.