In this paper, we report the first silicon-on-insulator (SOI) integration technique for organic field effect transistor (OFET) based circuits. Proposed design flow relies on only basic micro-fabrication processes such as photolithography and physical vapor deposition. This novel fabrication technique allows patterning of conductive silicon gate islands on the subtrate and eases the via and interconnect patterning and deposition for a bottom-gate OFET configuration. We fabricated pand n-type transistors, and proof of concept OFET-based complementary circuits such as inverter and NAND-gate. Fabricated CMOS inverters have full rail-to-rail swing, very high gain (up to 58.3 at 60V, and 18.1 at 20V supply voltages), and outstanding noise margins of around 21V symmetric for NMhigh and NMlow at 60V supply voltage.