The frequency synthesizer is one of the most challenging blocks in wireless transceivers; it works as a local oscillator in both the receiver and transmitter. It is generally based on a charge pump phase-locked loop (CPPLL) structure. If we can change the structure of the CPPLL or synthesizer to achieve fast locking, it can be used in applications to improve the locking time. Several methods have been introduced to increase the speed of the locking process. One way to achieve fast locking is to use a bang-bang frequency comparator (BBFC) in the feedthrough path to increase the locking speed. However, using the BBFC leads to unwanted ripple in the control voltage applied to the VCO; this ripple, in turn, leads to worse phase noise. In addition, an offset in the BBFC can produce cycle slipping. Applying a proper deadzone in the BBFC can help the system to overcome the unwanted ripple and cycle slipping. Simulations in MATLAB confirm that applying a deadzone equal to or larger than the frequency offset can suppress the unwanted ripple.