As the performance of computer systems improves, the peak bandwidth of the DRAM system needs to be increased. In this study, we analyze the performance of multi-bank DRAMs when increasing the clock frequency by employing three metrics: data bus busy time, bank busy time and inter-bank interference time. We use a cycle-accurate DRAM model simulator to quantitatively measure each metric. Increasing the DRAM clock frequency obviously contributes to lowering the data bus busy time. From the analysis result, we find that raising the number of banks is needed when increasing the DRAM clock frequency. However, the inter-bank interference time becomes the performance bottleneck as the number of banks increases. We suggest that future multi-bank DRAM system should tackle this side-effect to efficiently exploit the faster clock frequency.