This paper presents a CMOS track and hold amplifier (THA) designed and fabricated in a 130 nm CMOS technology. It is intended for analog-to-digital converters (ADCs) used in radio receivers that sample in the Giga-Hertz region. At these data rates, it is extremely difficult for data converters to reach the desired performance levels using a single data path. Rather, ADCs operating in parallel at lower clock rates are becoming the norm. Such architectures require high-performance THAs capable of capturing the signal information at the desired sampling speed. Experimentally, this work will demonstrate a 2.5 GS/s THA capable of offering an SNR of almost 46 dB, SNDR of 42.4 dB and an ENOB of almost 7 bits.