This paper describes the input dependent clock jitter in high speed and high resolution ADCs with a different approach as compared to previous works. There is always a capacitive coupling between the input and the clock signal paths through which the input voltage variation influences the clock and consequently produces jitter even if the sample and hold is assumed ideal and the clock itself is jitter-free. This phenomenon has been analyzed mathematically and then evaluated by simulations. Also the effect of the jitter on the output data has been explained. Results show that for high sampling rate more than 200 MHz this effect dominates and limits the SNR.