Loading [a11y]/accessibility-menu.js
Power optimization in a parallel multiplier using voltage islands | IEEE Conference Publication | IEEE Xplore

Power optimization in a parallel multiplier using voltage islands


Abstract:

Minimizing the power dissipation of parallel multipliers is important for mobile digital signal processing. In this paper, we present an approach to reducing power dissip...Show More

Abstract:

Minimizing the power dissipation of parallel multipliers is important for mobile digital signal processing. In this paper, we present an approach to reducing power dissipation in the design of parallel multipliers by utilizing voltage islands to exploit non-uniform arrival of inputs to the carry propagate adder. Our approach reduces up to approximately 20% of dynamic power dissipation with little delay penalty in a parallel multiplier of a tree type, and uses a fast simple adder instead of a hybrid adder.
Date of Conference: 19-23 May 2013
Date Added to IEEE Xplore: 01 August 2013
ISBN Information:

ISSN Information:

Conference Location: Beijing, China

References

References is not available for this document.