This paper presents a continuous-time quadrature bandpass ΔΣ ADC that achieves 60dB DR and 67.4dB SFDR at 1MHz BW and 1MHz IF. The modulator uses capacitive feedforward architecture for the 3^rd order loop filter for reduced power consumption and a local feedback loop for optimized noise shaping within the required band. The design is targeted for low power low IF receivers and it achieves a total power consumption of 1.7mW from 1.2V supply. The chip is fabricated with UMC 0.13μm technology.