This work discusses the design of a 60ps delay element for UWB analog signals ranging from 0.05 up to 8GHz. The design is implemented using active architecture design which have the advantage of being very compact in area compared to the passive architectures. The proposed architecture is flexible and can be cascaded to have a delay of up to 200ps with a maximum insertion loss of 3dB. The circuit is designed using a low cost 0.25μm 95GHz f_max SiGe-HBT-BiCMOS process technology consuming a power of 121mW. The estimated consumed area of the circuit is 0.49mm².