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Analysis and design of high speed/high linearity continuous time delta-sigma modulator | IEEE Conference Publication | IEEE Xplore

Analysis and design of high speed/high linearity continuous time delta-sigma modulator


Abstract:

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high...Show More

Abstract:

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.
Date of Conference: 19-23 May 2013
Date Added to IEEE Xplore: 01 August 2013
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Conference Location: Beijing, China

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