This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) to be used in the upgrade of the data acquisition electronics of the upgrade of the LHCb calorimeters. in order to shift the phase of the clock (25 ns) in steps of 1ns, with a 55ps jitter and 21.5ps of delay line linearity. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in AMS CMOS 0.35um technology.