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Full-stream architecture for ray tracing with efficient data transmission | IEEE Conference Publication | IEEE Xplore

Full-stream architecture for ray tracing with efficient data transmission


Abstract:

In this paper, we focus on the impact of a memory bandwidth limitation by analyzing the bandwidth consumption for a ray tracing system and present an energy efficient dat...Show More

Abstract:

In this paper, we focus on the impact of a memory bandwidth limitation by analyzing the bandwidth consumption for a ray tracing system and present an energy efficient data transmission method using a dedicated interface between the processor and ray tracing hardware engine. To achieve real-time ray tracing, we propose a full-stream architecture through the use of this dedicated interface. For an evaluation of our approach, we implemented a prototype ray tracing architecture using our approach on an FPGA platform. Our experimental results, indicate that our approach shows an average reduction in system memory bandwidth of 48% and an average performance improvement of 50%.
Date of Conference: 01-05 June 2014
Date Added to IEEE Xplore: 26 July 2014
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Conference Location: Melbourne, VIC, Australia

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