We propose a novel Variable-Delay Window ADC (VDWADC) design for digitally-controlled switched-mode dc-dc converters. In conventional Window ADCs based on the voltage-controlled delay line, the input voltage supplies the delay line. Thus, the conversion speed slows down when the input voltage decreases. The VDWADC is based on delay lines whose supply voltages are independent of the supply voltage. Hence, when the input voltage decreases, the conversion speed does not slow down. The VDWADC is simulated using 180 nm CMOS process and a supply voltage of 1.8 V. It achieves a quantization step of 0.05 V, or equivalently, a resolution of ~5.2 bits.