Loading [a11y]/accessibility-menu.js
Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit | IEEE Conference Publication | IEEE Xplore

Design of a low-noise, high power efficiency neural recording front-end with an integrated real-time compressed sensing unit


Abstract:

This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The pro...Show More

Abstract:

This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing unit. A capacitor coupled instrumentation amplifier integrated input impedance boosting has been designed, dissipating 1μA quiescent current. An input referred noise of 1.63μV was measured in the frequency band of 1Hz to 7kHz. The noise efficiency factor (NEF) of the amplifier is 0.76. The SAR ADC achieves an ENOB of 10.6-bit at a sampling rate of 1MS/s. A compressed sensing processing unit with configurable compression ratio, up to 8x, was integrated in the design. The design has been fabricated in 180nm CMOS, occupying 4.5mm×1.5mm silicon area. A portable neural recorder has been built with the custom IC and a commercial low-power wireless module. A 4.6g lithium battery supports the device for a continuous compressed sensing recording up to 70 hours.
Date of Conference: 24-27 May 2015
Date Added to IEEE Xplore: 30 July 2015
Electronic ISBN:978-1-4799-8391-9

ISSN Information:

Conference Location: Lisbon, Portugal

Contact IEEE to Subscribe

References

References is not available for this document.