Using a switched capacitor DAC in the feedback path of a continuous-time ΔΣ modulator reduces the sensitivity of the modulator to clock jitter. However, the peak to average ratio of the feedback waveform is large, thereby degrading the linearity of the modulator. The recently proposed dual switched capacitor resistor (DSCR) DAC aims to address this problem. This brief analyzes some interesting properties of this DAC, which have not been recognized in prior work. In particular, we show that using an DSCR DAC has excellent alias rejection around odd multiples of the sampling frequency. The intuition, theory and simulations that confirm this phenomenon are given.1