In this paper, we introduce a method for realizable reduction of extracted RC netlists by merging nodes. This method can achieve high reduction (reaching 96%) with high accuracy and can be used to complement existing techniques of realizable reduction such as TICER [6]. The method preserves sparsity; has controllable accuracy and can result in lossless reduction (exact reduction) for certain circuits. The node merging translates to a simple matrix operation and thus can be easily adopted commercially and realized in CAD tools.