A 1.2-V 42.3-μW three-stage amplifier capable of driving 0.5-to-15-nF capacitive load is proposed. By removing the inner Miller capacitor and adopting cascode Miller compensation in the outer feedback loop, the complex-pole frequency is extended effectively and the size of the compensation capacitors is reduced. Moreover, the Q-factor is reduced by paralleling a small Miller capacitor to the cascode compensation block. Furthermore, the presence of two left-half-plane zeros created by feedforward transconductance stage and cascode Miller capacitor in the proposed topology can improve the stability and slew rate of the amplifier. Implemented in 0.13-μm CMOS technology, the simulated gain-bandwidth product (GBW), slew rate (SR) and phase margin when driving a 15-nF capacitor are 1.13 MHz, 0.16 V/μs and 37°, respectively.