This work proposes asynchronous interleaved scan architecture (AISA) intended for the internal structure of online Built-in Self-test for Null Convention Logic (NCL) circuits. NCL is a robust asynchronous paradigm which can target devices for long-life missions and hard-to-access environments. However, on-line self-test methods adapted to match the characteristics of this important asynchronous method are not available currently. Existing test hardware for NCL is based on synchronous test elements. Such test hardware when used for on-line testing could introduce metastability issues and reduce the reliability of the highly robust NCL devices. We propose a scan architecture specifically designed for NCL circuits and demonstrate how this can be integrated into an on-line BIST architecture. Results for timing of the scan cell are shown with an average area overhead of 10%, which is only 35% of that of previous work [1]. Furthermore we do not need clock trees or double latches for sync/async interfaces.