For the last decades, the advancement of system on chips complexity and size are driving the verification process of the digital designs to be much more complicated and time consuming. Moreover, nowadays, the verification process takes up to 80% of overall design development time. This paper emphasizes the importance of automatic testbench generator for industrial wireless local area network (iWLAN) for factory automation system (FA). The proposed generated testbench is written in SystemVerilog to represent the functions and to reduce the code size compared to traditional Verilog testbench. It is also supported by assertion-based method to simplify the code and to improve the observability in SoC verification. Experimental results show that our proposed method produces smaller code size and can improve the efficiency of the verification of SoC designs. Moreover, we shows the verified iWLAN system data transfer.