Deep learning neural networks optimization using hardware cost penalty | IEEE Conference Publication | IEEE Xplore

Deep learning neural networks optimization using hardware cost penalty


Abstract:

As deep learning neural networks (DNNs) advance and increase in computational complexity, particularly in terms of memory cost, it becomes difficult to implement DNNs in ...Show More

Abstract:

As deep learning neural networks (DNNs) advance and increase in computational complexity, particularly in terms of memory cost, it becomes difficult to implement DNNs in fixed-point memory-sparse environments (e.g. integrated circuits in consumer electronics). Thus, the training of DNNs must be reformulated to balance the hardware costs needed to represent the often millions of parameter weights in such machine learning models. This paper proposes a novel optimization approach that simultaneously minimizes complexity (total memory) and maximizes accuracy. Specifically, a bit-depth complexity penalty is induced to urge the DNN model towards a state of lower memory using a numerical gradient in optimization iterations. Experimental results on the MNIST (Mixed National Institute of Standards and Technology) handwritten digit classification benchmark demonstrate a minimal loss (1%) in DNN accuracy with a significant reduction (37%) of memory cost on average.
Date of Conference: 22-25 May 2016
Date Added to IEEE Xplore: 11 August 2016
ISBN Information:
Electronic ISSN: 2379-447X
Conference Location: Montreal, QC, Canada

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