Digital harmonic-cancelling sine-wave synthesizers (DHSSs) enable programmable, low cost, spectrally pure, sinusoidal signal synthesis for application areas such as communication systems, and on-chip testing of analog/mixed-signal integrated circuits. The implementation of a DHSS requires a digital-to-analog converter (DAC). However, unlike a conventional binary-coded DAC, the harmonic-cancelling DAC (HC-DAC) used in a DHSS scales the input digital signals by a set of irrational amplitude weights. Consequently, the conventional knowledge of how amplitude resolution affects a binary-coded DAC does not apply to HC-DACs. In this paper, we present a mathematical study of how amplitude resolution and unit-element mismatch affects the signal-to-distortion (SDR) ratio of an HC-DAC. The results of the study show that it is possible to find a Pareto optimal value of amplitude resolution for a given HC-DAC with a target SDR. The values of SDR estimated from the mathematical model have been verified against circuit simulation results from two HC-DAC designs created using a 013 μm CMOS technology.