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Post-processing of supergate networks aiming cell layout optimization | IEEE Conference Publication | IEEE Xplore

Post-processing of supergate networks aiming cell layout optimization


Abstract:

Recently, methods for switch network generation have gain relevance. The main goal of these techniques is to minimize the number of transistors in the logical arrangement...Show More

Abstract:

Recently, methods for switch network generation have gain relevance. The main goal of these techniques is to minimize the number of transistors in the logical arrangement. However, theses methods do not consider optimizations at layout level. In this paper, we propose a post-processing technique in a state-of-art method for network generation to improve some layout aspects such as area, delay, power and parasitic capacitance. Experiments performed over a well-known benchmark demonstrate that the proposed technique allows average gains of 7.48% and 8.48% in the cell area and wirelength, respectively. Electrical characterization results have also shown improvements for propagation delay, transition delay, leakage and switching power in 4.18%, 4.94%, 7.52% and 12.40%, in that order.
Date of Conference: 28-31 May 2017
Date Added to IEEE Xplore: 28 September 2017
ISBN Information:
Electronic ISSN: 2379-447X
Conference Location: Baltimore, MD, USA

References

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