The conventional dummy fill insertion operation is usually conducted by foundries without taking into account circuit performance. In this paper, we propose a graph-based scheme to first modify layout interconnect geometry to improve pattern density uniformity in the analog layouts before the traditional dummy fill insertion process as an optional stage. The original analog constraints can be still preserved thanks to the mechanism of the constraint graphs used to represent the analog layouts. The experimental results show that our proposed method can improve pattern density uniformity by up to 75% for the regular analog layouts.