The printability problem of chip making becomes challenging in advanced process nodes. At present, various lithography technologies such as multiple patterning (MP), directed self-assembly (DSA), electron beam (e-beam), and their combinations are being considered. In this paper, the corresponding layout decomposition problems for contact/via generation are studied. In particular, we investigate the simultaneous DSA template and e-beam throughput optimization. First, we present an exact method based on an ILP formulation. Then, a graph-based algorithm is developed. The co-optimization problem for DSA double patterning with e-beam is formulated as a minimum hitting set problem. A primal-dual based algorithm is then derived for solving the problem effectively. Experimental results show that compared with a two-stage method, our method can achieve around 20.6% throughput improvement and 18.7% template cost reduction.