In this paper, we present a designed single Magnetic Tunnel Junction (MTJ) cell and a single switching transistor (1T-1MTJ) bitcell based 8Mb 64 I/O Spin-Transfer-Torque Magnetic RAM (STT-MRAM). Novel 3-Section Symmetric Reference Structure and high-gain Single-stage cross-coupled Sense Amplifier (SA) are implemented. The developed chip has about 40% decreased area and power consumption when compared to the same process 2T-2MTJ STT-MRAM or SRAM chips with equal memory bit size. The achieved read time is lesser than 10ns at worst MTJ and Process-Voltage-Temperature corner. Failed bit counts are fewer by 1.7% for MTJ's Tunnel Magneto-Resistance (TMR) higher 150%. This chip has demonstrated complete SRAM compatibility by passing all the tests in the display TCON (Time Controller).