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Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques | IEEE Conference Publication | IEEE Xplore

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques


Abstract:

Reliability concerns arise in nonvolatile magnetoelectric random access memory (MeRAM) due to continuously nanotechnology scaling down and CMOS-magnetic hybrid integratio...Show More

Abstract:

Reliability concerns arise in nonvolatile magnetoelectric random access memory (MeRAM) due to continuously nanotechnology scaling down and CMOS-magnetic hybrid integration. The primary objective of this work is to investigate failure mitigation in voltage-controlled magnetic anisotropy-magnetic tunnel junction (VCMA-MTJ) based 1T-1MTJ MeRAM bit-cell, by using MTJ compact model and 28nm fully depleted silicon on insulator (FD-SOI) process design-kit. A comprehensive reliability study is performed considering process variation and aging degradations, including hot carrier injection (HCI), bias temperature instability (BTI), soft breakdown (SBD) and radiation effect. Write assist techniques are proposed to ensure failure resilient MeRAM design. Bit line (BL) boost and negative source line (SL) methods show high efficiency in writing latency improvement and failure mitigation.
Date of Conference: 27-30 May 2018
Date Added to IEEE Xplore: 04 May 2018
ISBN Information:
Electronic ISSN: 2379-447X
Conference Location: Florence, Italy

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