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An Efficient Hardware Architecture for the Implementation of Multi-Step Look-Ahead Sigma-Delta Modulators | IEEE Conference Publication | IEEE Xplore
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An Efficient Hardware Architecture for the Implementation of Multi-Step Look-Ahead Sigma-Delta Modulators


Abstract:

A hardware architecture for the implementation of Multi-Step Look-Ahead Sigma-Delta Modulators (MSLA SDMs) is presented. MSLA SDMs offer superior performance than convent...Show More

Abstract:

A hardware architecture for the implementation of Multi-Step Look-Ahead Sigma-Delta Modulators (MSLA SDMs) is presented. MSLA SDMs offer superior performance than conventional single-bit SDMs for a multitude of applications relying on single-bit signal representation. However, traditional look-ahead SDMs have very high algorithmic complexity and their hardware implementation does not allow for real-time operation. MSLA SDMs overcome this problem by transforming the minimization problem associated with traditional look-ahead SDMs. A proof-of-concept FPGA implementation of a specific MSLA SDM is discussed and compared to a conventional single-bit SDM in terms of performance and hardware complexity. It is demonstrated that MSLA SDMs are a viable alternative to conventional single-bit SDMs when better performance with moderate additional hardware complexity are required.
Date of Conference: 27-30 May 2018
Date Added to IEEE Xplore: 04 May 2018
ISBN Information:
Electronic ISSN: 2379-447X
Conference Location: Florence, Italy

References

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