An optimization technique is proposed to set the supply voltage of an integrated circuit for a given range of threshold voltages. The algorithm accounts for the variations in maximum operating frequency f_max, noise margins, and threshold voltage. The algorithmically determined supply and threshold voltages are compared with SPICE simulation for a 130 nm CMOS technology, where per cent error of up to 14% and 8% are observed for, respectively, the average noise margins NM_avg and f_max as compared to target circuit specifications for noise margin and frequency. The evaluated ranges of the supply and threshold voltages are, respectively, 200 mV ≤ V_dd ≤ 1200 mV and 250 mV ≤ V_t ≤ 700 mV. The technique is applied to both a 130 nm and 45 nm CMOS technology and results of noise margin and frequency are compared through SPICE simulation. The 45 nm technology node exhibits variation of up to 0.89× and 4.3× in, respectively, NM_avg and f_max as compared to an inverter in a 130 nm technology.