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Transient Clock Power Estimation of Pre-CTS Netlist | IEEE Conference Publication | IEEE Xplore

Transient Clock Power Estimation of Pre-CTS Netlist


Abstract:

Clock tree synthesis (CTS) is performed in a very late stage of design. Power estimation, therefore, can only be done without clock network in most design stages, which i...Show More

Abstract:

Clock tree synthesis (CTS) is performed in a very late stage of design. Power estimation, therefore, can only be done without clock network in most design stages, which is not desirable given that clock network is usually the biggest power consumer. One may adopt an estimate of clock power, but its dynamic nature arising from clock gating brings a challenge in the estimation of clock power in a pre-CTS design. In this paper, we (1) estimate the clock tree components (clock gating cells (CGCs) and buffers as well as their wireloads) by using artificial neural networks (ANNs) and (2) use them while gating or ungating of each CGC is identified from a netlist cycle-by-cycle to estimate transient clock power consumption. Experiments with a few test circuits indicate that (1) the estimation of clock tree components causes the error of 13% on average, and (2) the estimated clock power waveform is very close to the actual waveform with average error of only 2%.
Date of Conference: 27-30 May 2018
Date Added to IEEE Xplore: 04 May 2018
ISBN Information:
Electronic ISSN: 2379-447X
Conference Location: Florence, Italy

References

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