Effect of Circuit Non-Idealities on Active On-Chip Delay Lines | IEEE Conference Publication | IEEE Xplore

Effect of Circuit Non-Idealities on Active On-Chip Delay Lines


Abstract:

Integrated circuit (IC) active all-pass filters with (almost) linear phase can provide large, wideband delays while consuming small chip area, and offer an alternative to...Show More

Abstract:

Integrated circuit (IC) active all-pass filters with (almost) linear phase can provide large, wideband delays while consuming small chip area, and offer an alternative to the bulky passive element based delay lines. However, they suffer from transconductor non-idealities like non-zero output conductance, mismatch between the transconductors, and non-negligible interconnect resistances in an IC. This paper presents an analysis of the effect of each of these, on the all-pass filter's transfer function. It is shown that under certain conditions, the large output conductance of the transconductors reduces the in-band gain of the filter uniformly and leaves the group delay unaffected. Mismatch between the transconductors forming the LC ladder in a higher order singly terminated filter causes group delay fluctuations but leaves the magnitude response unaffected, and the finite interconnect resistances introduce magnitude droop at the band-edge of the filter without affecting the delay response significantly.
Date of Conference: 26-29 May 2019
Date Added to IEEE Xplore: 01 May 2019
Print ISBN:978-1-7281-0397-6
Print ISSN: 2158-1525
Conference Location: Sapporo, Japan

Contact IEEE to Subscribe

References

References is not available for this document.