This paper characterizes experimentally the aging degradation experienced by two different 2.45 GHz power amplifier circuits of similar performance, implemented in a 65 nm CMOS technology. Results demonstrate the importance of the topology selection in order to guarantee robustness against aging effects, and thus the need to predict MOS parameter degradation during the design phase, accounting for the actual DC and RF operation conditions. For that purpose, we propose a semi-empirical compact model that, based on the RMS equivalent voltages at the transistor terminals during circuit operation, can provide an estimation of the aging degradation.