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A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology | IEEE Conference Publication | IEEE Xplore

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology


Abstract:

Systems on Chip for the Internet of Things require fast-locking and robust clock generators to maximize the effectiveness of power management techniques such as Dynamic V...Show More

Abstract:

Systems on Chip for the Internet of Things require fast-locking and robust clock generators to maximize the effectiveness of power management techniques such as Dynamic Voltage and Frequency Scaling and duty-cycling. We present an ADPLL clock generator based on a fully digital DCO architecture with an inherently linear and offset-free tuning characteristic that allows fast lock-in within three and frequency changes during operation within two reference cycles. Measurements from a testchip in 22nm FDSOI CMOS technology show operation from 0.4 to 0.8 V and 20 to 790 MHz. At 0.5 V, only 107 μW are consumed to generate a 100 MHz clock with 59 ps RMS period jitter. Adaptive Body Biasing improves the jitter performance by up to 40% through compensation of PVT variation.
Date of Conference: 26-29 May 2019
Date Added to IEEE Xplore: 01 May 2019
Print ISBN:978-1-7281-0397-6
Print ISSN: 2158-1525
Conference Location: Sapporo, Japan

References

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