This paper presents a multi-bit phase-frequency detector (PFD) architecture with self-calibration scheme to reduce the jitter in all-digital phase-locked loops. A standard bang-bang PFD is extended by two additional PFDs which allow the measurement of the ADPLL jitter distribution width. A built-in self-calibration algorithm can utilise this feature to optimise the loop filter gain for minimised overall jitter. The proposed technique is demonstrated in hardware within an LC-ADPLL in 28 nm SLP CMOS technology with 7.5 GHz output from a reference frequency of 100 MHz. By using the proposed PFD technique the total accumulated jitter is reduced by 20%.