We design an efficient DMA controller for scientific computing accelerators. It supports several flexible and powerful transfers, including reshape transfers, parameter linking mechanism, and transfer chaining meachnism. We also optimize the DMA controller for critical scientific computing kernels. It supports high bandwidth matrix transposition during data movement. It improves the memory access efficiency for matrix multiplication. Experimental results show that the data movement bandwidth achieved by the DMA controller is similar to the theoretical maximum one. It also performs very closely to an ideal design for real applications.