Recent trends in the field of artificial neural networks (ANNs) and convolutional neural networks (CNNs) investigate weight binarization for full on-chip weight storage to minimize circuit resources and to avoid the high energy cost of off-chip memory accesses. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning targets applications constrained in power and resources during the training phase. However, leveraging high-density on-chip online learning in binary-weight SNNs is still an open challenge. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm² in 65nm CMOS, achieving a high density of 738k synapses/mm².