Recent state-of-the-art designs have shown that high jitter robustness and low integrator dynamics, thus better linearity can be achieved in a single-bit continuous-time (CT) delta-sigma (ΔΣ) modulator by adapting a finite impulse response (FIR) filter in the feedback digital-to-analog converter (DAC). However, when applying this to CT incremental ΔΣ modulators, after each periodic reset of the loop-filter, the output of each FIR tap is unrelated to the input signal and a certain amount of time is needed to settle back to a normal operation. This results in a severe swing overshoots at the output of the integrators in the initial phase of every incremental ΔΣ conversion cycle, which limits the dynamic range (DR) of the modulator and thus counteracts the benefits of the FIR DAC. This paper describes the challenges that come with acquiring an FIR DAC in an incremental ΔΣ modulator. Additionally, two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator. This allows higher number of FIR taps to be used in an incremental ΔΣ modulator, which is very beneficial to promote high speed/resolution designs.