Abstract:
This paper describes an energy-security scalable crypto-core for private-key cryptography in low-end sensor nodes based on SIMON cipher. Energy and area footprints are re...Show MoreMetadata
Abstract:
This paper describes an energy-security scalable crypto-core for private-key cryptography in low-end sensor nodes based on SIMON cipher. Energy and area footprints are reduced through techniques at the algorithm, microarchitectural and gate level. At the algorithm level, multiple encryption is introduced to dynamically expand the key length from 64 to 256 bits at minimal reconfiguration complexity, allowing shorter keys and lower energy when lower level of security is demanded. The 1-round parallel architecture with short 32-bit datapath narrows the traditionally large gap between the conventional crypto-core data (e.g., 128 bits) and low-end processors (32 bit or lower), mitigating or eliminating the need for area- and energy-hungry FIFO buffers at their interface. At the gate level, the adoption of multi-bit pulsed latch-based pipelines with internal clock buffer sharing reduces the dominant clock power/area contribution of sequential elements. Tunable clock duty cycle allows time borrowing for improved variation resilience at ultra-low voltages at low hold-fix buffer count, leveraging the inherent margin against hold time violations enabled by relatively uniform pipestage delays. A 40 nm testchip shows energy down to 0.31 pJ/bit at 0.45 V with 64-bit key and 0.79E6 F2 area (F = process minimum feature size). The proposed crypto-core is well suited for ubiquitous security in energy/area-constrained platforms (e.g., low-end sensor nodes, RFIDs), while preserving full 256-bit security when necessary.
Date of Conference: 12-14 October 2020
Date Added to IEEE Xplore: 28 September 2020
Print ISBN:978-1-7281-3320-1
Print ISSN: 2158-1525