In this work, we introduce bitcell array-based support parameters to improve the prediction accuracy of SRAM-based binarized neural network (SRAM-BNN). Our approach enhances the training weight space of SRAM-BNN while requiring minimal overheads to a typical design. More flexibility of the weight space leads to higher prediction accuracy in our design. We adapt row digital-to-analog (DAC) converter, and computing flow in SRAM-BNN for bitcell array-based weight supports. Using the discussed interventions, our scheme also allows a dynamic trade-off of accuracy against energy to address dynamic energy constraints in typical real-time applications. Our approach reduces classification error in MNIST from 1.4% to 0.91%. To reduce the power overheads, we propose a dynamic drop out of support parameters, which also reduces the processing energy of the in-SRAM weight-input product Our architecture can dropout 52% of the bitcell array-based support parameters with only minimal accuracy degradation. We also characterize our design under varying degrees of process variability in the transistors.