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AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration | IEEE Conference Publication | IEEE Xplore

AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration


Abstract:

The RISC-V open source instruction set architecture is a promising solution for applications related to low power embedded systems. This paper presents a configurable RIS...Show More

Abstract:

The RISC-V open source instruction set architecture is a promising solution for applications related to low power embedded systems. This paper presents a configurable RISC-V processor architecture providing a compromise between the number of clock cycles required to execute an instruction, the maximum operating frequency, the resource utilization and the power consumption. This architectural flexibility enables the processor to be adapted to fit application constraints, on either FPGA or ASIC targets.
Date of Conference: 21-25 May 2023
Date Added to IEEE Xplore: 21 July 2023
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Conference Location: Monterey, CA, USA

References

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