This paper describes a 108 mega pixels (Mp) CMOS image sensor (CIS) for mobile phone applications. The 0.7 $\mu$m-pitch pixel array ($12000\times 9000$) is composed of nona-cell ($3\times 3$ unit pixel structure) cluster with binning capability for maximum light absorption. In considerations of the trade-off between area occupation and frame rate, the column-parallel topology with thousands of single-slope ADCs is chosen for the digitizer. To suppress the horizontal noise (HN) source, an ADC decision-feedback technique is proposed to minimize the current consumption difference between before and after the ADC decision. Furthermore, with the decision-feedback loop, which is implemented in each of the comparators of the ADC array, analog power consumption can be also reduced. Top pixel and bottom digitizer chips were fabricated in 65 nm and 28 nm process technologies, respectively. The measurement results of the 3-D stacked prototype imager show an input-referred random noise (RN) of 1.4 $\mathrm{e}_{\mathrm{rms}}^{-}$ with an analog gain of 16 and a frame rate of 10 fps. A suppressed RN of 0.44 $\mathrm{e}_{\mathrm{rms}}^{-}$ is also achieved with a nona-binning. The column fixed-pattern noise (FPN) of the 108 MP imager is only 66 ppm. The high-resolution image sensing system with the decision-feedback technique achieves a figure-of-merit (FoM) of 0.71 e.nJ.