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Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops | IEEE Conference Publication | IEEE Xplore

Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops


Abstract:

Since the width of flip-flop standard cells is relatively much longer than that of the cells of primitive gates, the impact of flipping flip-flop cells horizontally in th...Show More

Abstract:

Since the width of flip-flop standard cells is relatively much longer than that of the cells of primitive gates, the impact of flipping flip-flop cells horizontally in the placement on routing complexity and timing is significant. However, as yet, no work has addressed the issue of how we can effectively exploit the well-known cell flipping technique to multi-bit flip-flop cells in placement. To this end, in this work, we introduce a concept of D-to-Q signal flipping for cell instances of multi-bit flip-flop where the directions of D-t-O signal flow of the individual flip-flop instances can be controlled separately and independently. Then, we propose an effective multi-bit cell flipping methodology based on the D-to-O signal flipping concept with the objective of enhancing routing complexity as well as timing slack in the placement optimization stage.
Date of Conference: 27 May 2022 - 01 June 2022
Date Added to IEEE Xplore: 11 November 2022
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Conference Location: Austin, TX, USA

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