Abstract:
A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves as a residual amplifier offering high bandwidt...Show MoreMetadata
Abstract:
A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves as a residual amplifier offering high bandwidth and superior power efficiency over conventional operational amplifier. A high linearity front-end is proposed to mitigate the non-linearity of the ESD diode and provide sufficient driving ability. In addition, it can reject the kickback noise from the core ADC. A digital background calibration method with digital-mixing is adopted to fix the mismatches among channels. The measured SNDR/SFDR with a low-frequency of the prototype ADC are 51.0/68.0 dB, achieving a competitive FoMw of 0.48 pJ/conv.-step at 2.5 GS/s.
Date of Conference: 27 May 2022 - 01 June 2022
Date Added to IEEE Xplore: 11 November 2022
ISBN Information: