Trapping and detrapping of charges in the oxide interface of a metal oxide semiconductor field effect transistor (MOSFET) leads to a random telegraphic noise (RTN) injection and this phenomenon negatively affects the reliability of stored bit in an SRAM cell. Reliability of bit stored in an SRAM cell is often measured by mean time to failure (MTTF). In this work, a method to estimate the statistical distribution of time to failure of a stored bit in an SRAM cell is proposed. The proposed method includes a composition of a trapping/detrapping current injection model, a Monte-Carlo simulator, and a circuit-level abstraction of an SRAM cell. As an example of the proposed method, using circuit-level simulations, the effect of RTN due to a single-trap model is showcased for 45 nm CMOS technology. As anticipated, the SRAM time to fail distribution worsens with a reduction in the supply voltage or with increase in process variations. More importantly, the time to fail distribution and its worsening have been numerically estimated using the proposed method.