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A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance | IEEE Conference Publication | IEEE Xplore

A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance


Abstract:

This paper presents a bootstrapped switch with an accelerated gate-voltage rising speed and a reduced on- resistance for high-speed ADCs. Compared to the classic bootstra...Show More

Abstract:

This paper presents a bootstrapped switch with an accelerated gate-voltage rising speed and a reduced on- resistance for high-speed ADCs. Compared to the classic bootstrapped switch, this design accelerates the rising speed of gate voltage through four novel techniques. First, an extra NMOS transistor is added to pull up the gate voltage by injecting extra charges into the gate node. Second, the parasitic capacitance at the gate node is reduced by simplifying the circuit structure, leading to a faster speed. Third, transmission gates are used to reduce the two delays to one delay. Fourth, the voltage stored on the capacitor is increased to slightly larger than VDD, which leads to a faster gate-voltage rising speed as well as a larger value of gate voltage (about Vn+1.05 VDD). The larger gate voltage also helps reduce the on-resistance of the bootstrapped switch, which is helpful for the high-speed sampling of ADCs. In a 40 nm CMOS process, post-layout simulation results show that the rising speed of gate voltage is increased by 3.3 times compared to the classic thin-oxide bootstrapped switch circuit. And the on-resistance of the bootstrapped switch is reduced by 2.2 times compared to the classic structure, due to the larger gate voltage value.
Date of Conference: 22-28 May 2021
Date Added to IEEE Xplore: 27 April 2021
Print ISBN:978-1-7281-9201-7
Print ISSN: 2158-1525
Conference Location: Daegu, Korea

Funding Agency:


References

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