Non-volatile ferroelectric field-effect transistor (FeFET) technology is a promising CMOS process compatible solution for fast, energy efficient on-chip memories that are needed to enable ubiquitous deployment of AI. Existing memories are linear by design and the bandwidth may not be sufficient to support transformers that underlie the now-popular Large Language Models (LLMs) for generative AI, which require fast accesses to matrices and their transposes. In this work, two designs of transposable FeFET memories are proposed to address this challenge. We evaluate our designs using compact models for the FeFET devices, which we have calibrated to experimentally measured device characterization data. We demonstrate that 1 ns read latencies are possible, which underscores the potential of FeFET technology for AI accelerators. The area efficiency of our proposed dual-gated transposable memory and the speed of transpose operations are studied, showing that it occupies 30.02 F ² cell area and is capable of maximum 82.24× faster transpose operation compared to non-transposable memory.