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αΩHighway interconnection network architecture for high performance computing | IEEE Conference Publication | IEEE Xplore

αΩHighway interconnection network architecture for high performance computing


Abstract:

The interconnection network is a crucial part of high-performance computer systems. It significantly determines parallel system performance as well as the development and...Show More

Abstract:

The interconnection network is a crucial part of high-performance computer systems. It significantly determines parallel system performance as well as the development and the operating cost. In this paper we suggest efficient and scalable hierarchical multi-ring interconnection network architecture. For building up the interconnection network we have designed adequate switch architecture and implemented “step-back-on-blocking” flow control algorithm. The architectural model has been verified and communicational performance parameters have been evaluated on the basis of numerous simulation experiments conducted in the OMNeT++ simulation environment.
Date of Conference: 01-04 July 2012
Date Added to IEEE Xplore: 26 July 2012
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ISSN Information:

Conference Location: Cappadocia, Turkey

References

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