With miniaturization of semiconductor manufacturing process, line spacing becomes narrower and hence the influence of coupling capacitance cannot be ignored. The signal delay on a defective line is affected by the signal transitions on its adjacent lines through the coupling capacitance. In addition, the delay size depends on the timing skew between signal transitions on the defective line and its adjacent lines. In test pattern generation, not all adjacent lines are required to have signal transitions to excite the fault effect if a large relative timing skew exists between the faulty line and the adjacent line. In this paper, we propose a selection method of adjacent lines for assigning signal transitions in test pattern generation. The proposed method can reduce the number of adjacent lines used in test pattern generation without degrading the quality of test pattern that can excite the fault effect.